The present invention relates to a data transfer control device and an electronic instrument.
Various interfaces for high-speed serial transfer have recently attracted much attention as interfaces designed to reduce EMI noise, such as a low voltage differential signaling (LVDS) interface. Such high-speed serial transfer implements data transfer by making a transmitter circuit use differential signals to transmit data that has been made serial and making a receiver circuit perform differential amplification on the differential signals. There are known interfaces for such high-speed serial transfer, such as the digital visual interface (DVI).
With a data transfer control device that implements such high-speed serial transfer, it is desirable that the scale of data transfer is as small as possible. To ensure efficient data transfer in accordance with various different situations, on the other hand, it is desirable to have as many different types of packet for serial transfer.
However, if the number of types of packet for serial transfer increases, the data transfer control device will have to perform complicated processing in order to handle a large number of packets. For that reason, the data transfer control device must have a processor such as a microprocessor unit (MPU) incorporated therein, which increases the size of the data transfer control device.
If the serial transfer path is made multi-channel, information indicating that this is a split transfer can be included in each packet, as shown in FIG. 6C, and such packets can take a configuration in which the packets are split into multiple channels for transmission, as shown in FIG. 6A. However, if channel 1 is delayed more than channel 2 during the sending of the split data, the data that is received through channel 2 is not combined with the data that is received through channel 1 and is thus transmitted at a later stage. In addition, a configuration can be used in which information indicating that the next data to be transferred is part of a split transfer is included beforehand in the packet, as shown in FIG. 6B. However, placing this information relating to the next packet to be transferred into each packet necessitates complicated processing, leading to a deterioration in data transfer efficiency and increasing the scale of the circuit configuration.